A voltage regulator is a circuit that provides a constant DC voltage between its output terminals in spite of changes in the load current drawn from the output terminals and/or changes in the DC power supply voltage that feeds the voltage regulator circuit. FIG. 1A describes a simplified DC model of a voltage regulator. As shown in FIG. 1A, the equivalent circuit model of voltage regulators in DC domain can be described as an ideal voltage source VS in series with an internal source resistor RS. The resistor RS represents an equivalent series resistance calculated from non-ideal effects inside the voltage regulator. FIG. 1B illustrate a typical topology of linear regulators in accordance with the prior art.
When non-ideal effects, such as input offset voltage, etc., are not dominant and ignored, the resistor RS is basically equal to the output resistance of the regulator. As the load current IL increases, there may be a non-ideal voltage drop ΔVLDR (also referred to as the load regulation effect) across the source resistor RS as shown below in equation (1):ΔVLDR=RS×ΔIL  (1)As a result, the DC voltage drop ΔVLDR over the desired regulator output voltage VS is proportional to both the resistance RS and the change in load current ΔIL. FIG. 2A illustrates the load regulation effect in the DC domain (Load regulation vs. ILOAD), in accordance with the prior art. The load regulation effect in transient response in time domain is illustrated in FIG. 2B. Load regulation effect is a dominant factor determining the best accuracy a regulator can achieve over process corners for products, especially for high load current and low-voltage applications. The load regulation effect is proportional to the resistance RS, which is approximately equal to the output resistance of the regulator, ΔVLDR/ΔIL. This means that the load regulation effect is minimized when the output resistance of the regulator decreases. Based on the typical linear regulator topology shown in FIG. 1B, the closed-loop output resistance RO—REG, which is the actual output resistance of the regulator, can be described as:
                              R          O_REG                =                              R            O_op                                1            +            Aβ                                              (        2        )            RO—op refers to the open loop output resistance, A is the total gain of the regulator, and β is the feedback factor of the regulator. The total gain of the regulator is inversely proportional to the square root of the load current, Thus, as can be seen from equation (2), Ro_reg increases as the load current increases resulting in high load regulation effect. Therefore, the focus of load regulation effect issues has been on the increasing of loop gain to reduce output resistance of the voltage regulator. It can be seen from equation (2) that as Aβ increases, RO—REG decreases (i.e., RO—REG approaches zero).
In addition to reducing the load regulation effect, there is also a problem related to inter-connection voltage loss. Although inter-connection voltage loss is usually neglected by designers, the voltage loss due to resistors for inter-connection (including on-chip metal connection, off-chip bonding wire, metal connection, etc.) is another critical issue like the load regulation effect, which may cause significant effects in a heavy current load environment. FIGS. 3A and 3B illustrate typical connection resistance between a regulator and a load circuit where there is both an on-chip connection and an off-chip connection, in accordance with the prior art.